1. Field of the Invention
The present invention relates to a method and structure of accelerating image-sensing speed in a CCD image-sensing device.
2. Description of the Related Art
CCD image-sensing devices are widely applied in image processing systems and digital signal processing systems where they serve as shift registers or sequential memory devices with high density. For example, CCD image-sensing devices are utilized in scanners, digital cameras and copy machines.
For conventional scanners or contact image scanners, image processing components are comprised of CCD image-sensing devices. FIG. 1 shows the schematic structure of a conventional CCD image-sensing device. In general, a CCD image-sensing device is composed of the following: a row of image-sensing elements (P1xcx9cPn) for sensing light energy and generating charge packets proportional to the light intensity; a CCD analog shift register 10 with multiple register elements (SH1xcx9cSH2n) for receiving and registering (storing) charge packets in parallel; a plurality of shift-control electrodes (G1xcx9cG2n); and an output amplifier (OP) for converting each of the charge packets into proportional voltage level(s) (Vim). The CCD shift register 10 is controlled by two clock signals, "PHgr"1 and "PHgr"2, which serially shift the charge packets stored in the register elements to the output amplifier (OP).
FIGS. 2(a) to 2(e) show the charge transferring process in the traditional CCD shift register depicted in FIG. 1. FIG. 2(f) shows the waveforms of the clock signals "PHgr"1 and "PHgr"2. The clock signals "PHgr"1 and "PHgr"2 are coupled to shift-control electrodes G2a, and G2axe2x88x921 (1xe2x89xa6axe2x89xa6n) respectively.
FIG. 2(a) schematically depicts the structure of CCD shift register 10. For brevity, only 5 shift-control electrodes (G1xcx9cG5) are shown in the CCD shift register and the threshold voltage is displayed as 0. The 5 shift-control electrodes (G1xcx9cG5), and the p-type semiconductor substrate (hereinafter referred to as p-type substrate or Psub) together form 5 register elements (SH1xcx9cSH5).
FIG. 2(b) depicts the distribution of potential barriers (step barriers) in the p-type substrate Psub when at time t1, "PHgr"1 and "PHgr"2 are at voltage levels 0 and V respectively. The potential barriers beneath shift-control electrodes G1, G3, and G5 are higher than those beneath shift-control electrodes G2 and G4. Hence, the charge packets (depicted as dashed lines) will be stored in the regions beneath the shift-control electrodes G2 and G4 in the p-type substrate Psub (i.e., register elements SH2 and SH4).
FIG. 2(c) depicts the distribution of potential barriers in the p-type substrate Psub when at time t2, both "PHgr"1 and "PHgr"2 are at voltage levels V/2. The arrows in FIG. 2(c) demonstrate that when time changes from t2 to t3, the potential barriers beneath the odd numbered shift-control electrodes will decrease and those beneath even numbered shift-control electrodes will increase.
FIG. 2(d) depicts the distribution of potential barriers in the p-type substrate Psub when at time t3, "PHgr"1 and "PHgr"2 are at voltage levels 3V/4 and V/4 respectively. Hence, the charge packets stored beneath the register elements SH2 and SH4 are transferred to the regions beneath the shift-control electrodes G1 and G3 with lower potential barriers (i.e., register elements SH1 and SH3).
Lastly, FIG. 2(e) depicts the distribution of potential barriers in the p-type substrate Psub when at time t4, "PHgr"1 and "PHgr"2 are at voltage levels V and 0 respectively. During the period measured from t1 to t4, the charge packets are transferred one register element to the right. Similarly, during the periods from t5 to t6 and t7 to t8, the charge packets are also transferred one register element to the right.
The resolution of scanners generally is 600 dpi (dots per inch) or more. When a scanner with 600 dpi resolution scans a document of A4 size (width=21 cm, length=29.7 cm), the CCD image-sensing device used by the scanner must be comprised of at least 7016 (≅29.7 cm/2.54 cmxc3x97600) image-sensing elements and 14032 (7016xc3x972) register elements in order to receive and register the charge packets corresponding to the image(s) within the scanned document.
Vendors of CCD image-sensing devices generally provide standard products having more than 10000 image-sensing elements. For example, standard CCD image-sensing devices have 12800 image-sensing elements (P1xcx9cP12800) and 25600 register elements (SH1xcx9cSH25600). When the standard CCD image-sensing product applies a resolution of 600 dpi to an A4 sized document, only 14032 register elements (SH1xcx9cSH14032) actually receive and register charge packets corresponding to the image(s) of the scanned document. The charge packets in register elements (SH14033xcx9cSH25600) are generated by light leakage or some other disturbance and do not correspond to the image(s) of the scanned document. Therefore, the charge packets registered in register elements (SH14033xcx9cSH25600) are undesired and redundant. Yet inevitably, redundant charge packets appear in every image-sensing operation.
According to the descriptions in FIGS. 2(a) to 2(e), the charge packets are serially shifted out of the CCD shift register and transformed to corresponding voltage levels. After shifting out the charge packets registered in register elements (SH1xcx9cSH14032), the charge packets registered in register elements (SH14033xcx9cSH256000) are also serially shifted for a displacement of 14032 register elements, netting 11,568 redundant charge packets stored in register elements (SH1xcx9cSH11568). In order for the CCD image-sensing device to carry out further image-sensing operations, the redundant charge packets must be serially shifting out of register elements (SH1xcx9cSH11568). Otherwise, the remaining (redundant) 11568 charge packets will be added to the newly received 11568 charge packets (from the next scanned image within the document). If not previously disposed of, these remaining, redundant charge packets will cause subsequent scanned image(s) to be distorted. Therefore, to avoid disturbance of the 11568 remaining, desired charge packets, the current art requires additional processing time to serially shift the 11568 remaining charge packets out of the CCD shift register before the CCD image-sensing device carries out its next image-sensing operation. Of course, this additional operation slows down the overall scanning and processing speed(s) of the scanner.
Presently, one method is widely applied in the industry to reduce the additional time required for processing of the remaining charge packets. This method involves increasing the frequency of clock signals "PHgr"1 and "PHgr"2 when shifting out the remaining charge packets as a means to accelerate the shift operation of the remaining charge packets thereby reducing additional processing time. Clock signals "PHgr"1 and "PHgr"2 generally operate at a normal frequency to shift out the desired charge packets (registered in the register elements Sh1xcx9cSH14032). However, clock signals "PHgr"1 and "PHgr"2 must operate at increasingly higher frequencies to shift out the remaining (redundant) charge packets. Indeed, requiring clock signals "PHgr"1 and "PHgr"2 to operate between two frequencies leads to problems of control, increased circuit complexity and higher manufacturing costs.
To mitigate the above mentioned problems, the present invention utilizes a novel method and mechanism for use in CCD image-sensing devices which avoids image distortion without needing to shift the remaining (redundant) charge packets out of the CCD shift register. As a result, the processing and scanning speeds of CCD image-sensing devices and scanners can be accelerated. Attendant benefits include reduced circuit complexity and lower manufacturing costs.
One objective of the present invention is to provide a method for accelerating image sensing of CCD image-sensing devices. According to the method, after a CCD image-sensing device finishes serially shifting out the charge packets corresponding to the image of the desired sensed object(s), the CCD image-sensing device can repeat the operation for image-sensing without having to shift out remaining redundant or undesired charge packets.
Another objective of the present invention proposes a novel CCD image-sensing device that allows for significantly faster processing speed than is available in conventional CCD image-sensing devices.
The proposed method of accelerating image-sensing speed is appropriate for CCD image-sensing device(s) wherein the CCD image-sensing device has at least a plurality of image-sensing elements (P1xcx9cPn), a CCD shift register composed of multiple register elements (SH1xcx9cSH2n) and multiple shift-control electrodes (G1xcx9cG2n) corresponding to the register elements (SH1xcx9cSH2n). It is noted that the register elements SH1xcx9cSH2jxe2x88x922 (j less than n) only register charge packets that correspond to the desired image of the sensed object.
The method comprises the steps of:
(a) coupling shift-control electrodes G2jxe2x88x921 and G2j to a first potential and a second potential respectively, thereby creating a block unit composed of register elements SH2jxe2x88x921 and SH2j;
(b) coupling the odd numbered shift-control electrodes (G2, G3, G5,xcx9cG2jxe2x88x925, G2jxe2x88x923) to a first clock signal;
(c) coupling the even numbered shift-control electrodes (G2, G4, G6,xcx9cG2jxe2x88x924, G2jxe2x88x922) to a second clock signal;
(d) having the image-sensing elements (P1xcx9cPn) sense light reflected from a object falling thereupon and generating a plurality of charge packets proportional to the light intensity;
(e) registering the charge packets in register elements SH1xcx9cSH2;
(f) serially shifting out the charge packets registered in register elements SH1xcx9cSH2jxe2x88x922 from the CCD shift register in response to the first and second clock signals whereby the charge packets registered in register elements SH2j+1xcx9cSH2n, are prevented from being shifted into register elements SH1xcx9cSH2jxe2x88x922 by a block unit thereby allowing the CCD image-sensing device to carry out the next sensing operation without needing to shift out the redundant charge packets registered in register elements SH2j+1xcx9cSH2n;
(g) starting the next scanning operation whereby the image-sensing elements (P1xcx9cPn) sense again and generate a plurality of charge packets;
(h) repeating steps (e)xcx9c(g) for registering and shifting out charge packets.
The CCD image-sensing device according to the present invention at least comprises:
(1) a plurality of image-sensing elements (P1xcx9cPn) for sensing light energy falling thereon to generate a plurality of charge packets proportional to the light intensity;
(2) a CCD shift register made up of a plurality of register elements (SH1xcx9cSH2n) and a plurality of shift-control electrodes (G1xcx9cG2n) corresponding to the register elements (SH1xcx9cSH2n); wherein the register elements (SH1xcx9cSH2jxe2x88x922; j less than n) register only those charge packets corresponding to a sensed object""s desired image; and
(3) an output amplifier for converting the charge packets into proportional voltage levels.
In summary, the odd numbered shift-control electrodes (G1, G3, G5xcx9cG2jxe2x88x925, G2jxe2x88x923) are coupled to a first clock signal, and the even numbered shift-control electrodes (G2, G4, G6,xcx9cG2jxe2x88x924, G2jxe2x88x922) are coupled to a second clock signal whereby the charge packets registered in register elements SH1xcx9cSH2jxe2x88x922 are serially shifted out of the CCD shift register in response to the first and second clock signals.
It is noted that shift-control electrodes G2jxe2x88x921 and G2j are coupled to a first potential and a second potential respectively. This new aspect of the art allows register elements SH2jxe2x88x921 and SH2j to serve as a block unit thereby blocking the charge packets registered in register elements SH2jxe2x88x921xcx9cSH2n from being shifted forward into the register elements SH1xcx9cSH2jxe2x88x922.